1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a nonvolatile memory device.
2. Description of the Related Art
Digital media devices have recently emerged that conveniently use desired information anytime and anywhere. A variety of digital devices that are gaining acceptance require a storage medium that will keep taken images, recorded music, and various data in storage. Thus, much attention has been paid to a system on chip (SoC) technology in the non-memory semiconductor field according to a high integration tendency, and the world semiconductor companies are competing with each other to improve the SoC technology. The SoC technology refers to a technology for integrating all system techniques into one semiconductor. When the system design technology is not isolated, it will become difficult to develop a non-memory semiconductor portion.
One of main products in the SoC field where complex techniques are integrated is an embedded memory, and much attention is paid to a flash memory among the embedded memories. The flash memory may be divided into a floating gate type and a silicon-oxide-nitride-oxide-silicon (SONOS) control gate type. Recently, research has been rapidly conducted on the SONOS type. For reference, the SONOS-type flash memory is a nonvolatile memory device using a mechanism of trapping and de-trapping electrons or holes in or from a trap site of a material layer (for example, nitride).
FIG. 1 is a cross-sectional view of a conventional nonvolatile memory device.
Referring to FIG. 1, the conventional SONOS-type flash memory device will be described as follows. A memory gate MG in which a memory layer 105 and a gate electrode 106 are stacked is formed over a substrate 101. A spacer 107 is formed on both sidewalls of the memory gate MG. Source and drain regions 108 are formed in the substrate 101 at both sides of the memory gate MG. The memory layer 105 includes a tunnel insulating layer 102, a charge trap layer 103, and a charge blocking layer 104, which are sequentially stacked. The gate electrode 106 serves as a control gate.
However, the conventional nonvolatile memory device, that is, the SONOS-type flash memory device has a concern that an over-erase occurs during an erase operation. In order to solve this concern, an additional operation, such as recovery, other than basic operations (for example, program/read/erase operations) and a peripheral circuit for the additional operation may be needed. Thus, there is a limitation in reducing the size of the nonvolatile memory device. For reference, the embedded memory occupies a relatively small area in comparison to a standalone memory having a several-GB capacity. Therefore, in order to reduce the size of the embedded memory, it is more important to reduce the area (or size) of peripheral circuits such as a decoder, a charge pump, a control logic and the like rather than the size of the embedded memory.
Furthermore, the conventional nonvolatile memory device uses hot carrier injection (HCI) during a program operation. However, the HCI has a concern in that the distribution of charges trapped in the charge trap layer 103 is wide, and non-uniform distribution of electrons and holes within the charge trap layer 103, that is, charge trap mismatch, occurs. Thus, reliability including endurance may be degraded.
Furthermore, the HCI consumes a large amount of current during a program operation, and requires a large-sized charge pump to supply the current. Thus, the HCI may not be suitable for being applied to the embedded memory.